Paper
Number

Session
Code

Paper Title

Authors

3

W1D

Space-Time Diversity applied to Single-User Environments and MIMO Transmission Channels

Antonio Pascual Iserte, Miguel A. Lagunas Hernandez, Ana I. Perez Neira

4

W3F

An Integrated Pedagogical Approach for a Switching Power Supply Design: Example of Flyback

Philippe Dondon, J.M. Lequertier

6

T1P

Design of Linear-Phase Variable 2-D FIR Digital Filters Using Matrix-Array Decomposition

Tian-Bo Deng

8

M2F

Integer Division in Residue Number System

Badreddine Rejeb, Heiko Henkelmann, Walter Anheier

10

T2B

Semi-Custom VLSI Chip Implementation of a New Two-Dimensional Separable Median Filtering Algorithm

Ahmad A. Hiasat

11

W1P

On Algorithm for Phoneme Speech Recognition Using Nonlinear Signal Decomposition

Alexander M. Krot, Polina P. Tkachova

15

M2B

Multirate Digital Squarer Architectures

Fengqi Yu, Alan N. Willson, Jr.

16

M2B

A Comparative Study of the Behavior of NMOS and CMOS Digital Circuits under Substrate Noise

Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman

17

W3B

A Capacitance Meter Based on an Oversampling Sigma Delta Modulator and Its Application to Capacitive Sensor Interface

R. Gallorini, N. Abouchi

19

M1E

Analog System Design Problem Formulation on the Basis of Control Theory

Alexander Zemliak

20

T1F

A Compact and High Resolution A/D Converter for Sensors

Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino

21

M2D

VLSI-Based Parallel Architecture for Block-Matching Motion Estimation in Low Bit-Rate Video Coding

Donglai Xu, John Bentley

24

M2P

Current Mode AB Class WTA Circuit

Krzysztof Wawryn, Bogdan Strzeszewski

27

W1P

Regularization of Neural Networks for Improved Load Forecasting in Power Systems

Krzysztof Siwek, Stanislaw Osowski

29

T1A

A New Differential Current Conveyor and Its Application as a Four Quadrant Multiplier

Hesham F. Hamed, Ahmed El-Gaafary, Mostafa S. A. El-Hakeem

31

W1C

State-Space Equations for Regular and Strictly Topologically Degenerate LLTI Networks: the Implicit Tree-Tableau Method

Antonino M. Sommariva

32

T1G

A Learning Automata-Based Bus Arbitration Scheme for Scalable Shared-Medium ATM Switches

Mohammad S. Obaidat, G.I. Papadimitriou, A.S. Pomportsis

33

W1P

An Ultra High-Speed Compressor for Packet Networks

Ioannis Papaefstathiou

34

W1B

A 1.0 GHz Clock Generator Design with a Negative Delay Using a Single-Shot Locking Method

Chua-Chin Wang, Yih-Long Tseng, Rong-Sui Kao

37

M2F

Optimized Reconfigurable MAC Processor Architecture

Marios Iliopoulos, Theodore Antonakopoulos

38

T1C

Asymptotic Results for a Generalization of the Stirling Numbers of the Second Kind

Bruno Cernuschi-Frias

40

T1C

A System-Level Analysis of Robustness by Randomised Algorithms

Cesare Alippi

41

W1P

A Proof of the Non-existence of Universal Nonlinearities for Blind Signal Separation

Heinz Mathis

42

M2P

A Small Sized Trench Electrode IGBT having Improved Latch-up and Breakdown Characteristics for Power IC Systems

Ey Goo Kang, Seung Hyun Moon, Man Young Sung

43

W2D

Analysis of Superconducting Thin Film using an Approximate Model of the Current Distribution

M.F. El-Kordy, T.E. Taha, A.M. Gomaa

44

W1C

Perturbation Methods for Canceling Interference in CDMA Systems

Chun Chian Lu

45

M1D

Dynamical Intelligent Network based on Group Representation Theory

Hisato Fujisaka, Maki Akita, Mititada Morisue

46

M2E

Fast Half-Swing Inter-Plane Circuits for Clocked NOR-NOR PLAs

Chua-Chin Wang, Chih-Chiang Chiu, Yu-Tsung Chein

47

T1B

An Area-Saving 3-dimensional Decoder Structure for ROMs

Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen

48

T2C

Calibration of Mismatch Errors in Time Interleaved ADCs

Mikael Karlsson Rudberg

49

M2C

Analytic Model for Temperature-Dependent I-V Characteristics and Small-Signal Parameters of GaAs MESFETs

Marcello Pesare, Agostino Giorgio, Anna Gina Perri

50

W1C

Vector Analysis of Dielectric Waveguides Using Magnetic Field Finite Elements with Helmholtz Equation

M. Silveira, W.N. do Amaral Pereira, A. Gopinath

52

T1C

N Latency 2N I/O-Bandwidth 2D-Array Matrix Multiplication Algorithm

A.K. Oudjida, S. Titri, M. Hamarlain

53

M1D

Asynchronous Event Redirecting in Bio-Inspired Communication

Ph. Hafliger

54

W1P

Multi-Hierarchy Storage & Interactive User Interface for Intelligent Browsing of Super High Resolution Images

Irene Cheng, Anup Basu

56

M2P

Modelling and Simulation of Low-Power and Low-Voltage Delta-Sigma Modulators

Ana Rusu, Serban Lungu

58

M2P

Collapse of Lost Solution and Chaos in a Driven Piecewise Linear Rayleigh Oscillator

Isao Hishinuma

59

W1P

The Bifurcation Structure of Fractional-Harmonic Entrainments in the Forced Rayleigh Oscillator

Munehisa Sekikawa, Tetsuya Yoshinaga, Hiroshi Kawakami

60

T3D

Demonstration of Speed Enhancements on an Industrial Circuit Through Application of Non-zero Clock Skew Scheduling

Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman

61

M3A

Low Supply Voltage, Low Quiescent Current, ULDO Linear Regulator

Gregorio Bontempo, Tiziana Signorelli, Francesco Pulvirenti

62

M3B

Fast Implementation of the One Dimensional Discrete Cosine Transform Using the Residue Number System

Pedro G. Fernandez, J. Ramirez, A. Garcia, L. Parrilla, A. Lloris

63

T3C

A Special March Test to Detect Delay Coupling Faults for RAMs

Mohamed Azimane, Antonio Lloris Ruiz

64

W2E

A Novel Low-Voltage Floating-Gate CMOS Transconductance Amplifier with sinh (tanh) Shaped Output Current

Yngvar Berg, Snorre Aunet, Oivind Naess, Mats Hovin

65

M3A

A 0.3V Floating-Gate Differential Amplifier Input Stage With Tunable Gain

Yngvar Berg, Snorre Aunet, Oivind Naess, Henning Gundersen, Mats Hovin

66

W1D

A New Variable Step LMS Algorithm for Transform Domain

Radu Ciprian Bilcu, P. Kuosmanen, K. Egiazarian

67

T1P

Pipelined Digital Processor for Dynamical EIT Inverse Problem Solution

Marija Kacarska, S. Loskovska

68

T1P

Pipeline Multiprocessor Algorithm for Contingency Analysis in Power Systems

Marija Kacarska, D. Andonov, V. Glamocanin, B. Stojkovska

70

W1D

A Step-Size Control for Adaptive Filters Using a Sign-Based Estimation of the Normalized Excess Mean-Squared Error

Dani Lippuner, August N. Kaelin

71

M2P

Evolution of SI Circuit Performances With Technology Advances

Patricia Desgreys, Patrick Loumeau

72

M3F

Recursive Structure for Linear Filtering using Number Theoretic Transform

M. Bhattacharya, J. Astola

73

M3F

Fast Multipole Method based Extraction of PEEC Parameters

Giulio Antonini

75

T1P

Digital FIR Double Notch Filters

Miroslav Vlcek, Pavel Zahradnik

77

W1P

A Speckle Reduction Filter using Wavelet-Based Methods for Medical Imaging Application

Su Cheol Kang, Seung Hong Hong

78

W1P

New Natural Selection Process and Chromosome Encoding for the Design of Multiplierless Lattice QMF Using Genetic Algorithm

Ya Jun Yu, Yong Ching Lim

79

M3D

An Efficient VLSI Architecture for HMM-Based Speech Recognition

Jer Min Jou, Yeu-Horng Shiau, Chen-Jen Huang

80

T2F

Design of a Cycle-Efficient 64B/32B Integer Divider Using a Table-Sharing Method

Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang

81

M3F

Cascade Coefficient Number Systems Lead to FIR Filters of Striking Computational Efficiency

Jeffrey O. Coleman

82

M1D

Time-Frequency Analysis as a Tool for Improving Neural Detectors for Low Probability of False Alarm

Pilar Jarabo Amores, Manuel Rosa Zurera, Francisco Lopez Ferreras, Pablo Lopez Espi

83

M2A

New Approach to Filters and Group Delay Equaliser Transfer Function Design

Jan Vondras, Pravoslav Martinek

84

M1E

Fault Tolerant Routing Algorithm Based on Parallel Branching Method for Faulty Hypercubes

Salih Gunes, Nihat Yilmaz and Ercan Yaldiz

85

W1P

On the Analysis of Three-Conductor Transmission Lines Using Park Transformation

Sonia Leva, Adriano Paolo Morando

88

M2E

Logic Optimization of Circuits with Pre-defined Internal Don't Cares

J.C. Rau, J.H. Wang, S.C. Chang

90

W1B

High Data Rate Synchronizers Operating at Low Speed

Antonio D. Reis, Jose F. Rocha, Atilio S. Gameiro, Jose P. Carvalho

91

M2E

Synthesis of Data Transmission Circuits Starting from Behavioral HW Descriptions

Walter Lange, Wolfgang Rosenstiel

92

T1P

Asynchronous Multipliers with Variable-Delay Counters

Gianluca Coretta, Jordi Cortadella

93

T3C

On-line Calibration for Non-linearity Reduction of Delay-Locked Delay-Lines

F. Baronti, L. Fanucci, D. Lunardini, R. Roncella, R. Saletti

94

M2F

Fast Residue Arithmetic Multipliers Based on a Signed-Digit Number System

Shugang Wei, Kensuke Shimizu

95

T1P

A Contention-Alleviated Static Keeper for High-Performance Domino Logic Circuits

Shang-Jyh Shieh, Jinn-Shyan Wang, Yuan-Hsun Yeh

96

T1P

Design of Low-Power Domino Circuits Using Multiple Supply Voltages

Shang-Jyh Shieh, Jinn-Shyan Wang

99

T3B

A New Approach for On-line Optimisation of a Fuzzy Controller

Joseph Haggege, Mohammed Benrejeb, Pierre Borne

101

M2D

Real Time Image Processing with Reconfigurable Hardware

Miguel Angel Vega Rodriguez, Juan M. Sanchez-Perez, Juan A. Gomez-Pulido

103

M1A

Design and Optimization of a Low Jitter Clock-Conversion PLL for SONET/SDH Optical Transmitters

Johan D. van der Tang, Cicero S. Vaucher

104

T1P

A New Method to Implement CORDIC Algorithm

M.W. Kharrat, M. Loulou, N. Masmoudi, L. Kamoun

109

M2P

Method for Testing and Characterization of Analog-Digital System

V. Zagursky

110

M1G

Boost-type Power Factor Correction Systems with Three-level Sigma-Delta Modulation

E. Dallago, M. Passoni, G. Venchi

111

T3B

A Fuzzy Controller for Step-Up DC/DC Converters

Marcello Criscione, Gianluca Giustolisi, Antonio Lionetto, Massimiliano Muscara, Gaetano Palumbo

113

W1P

Development of a Vision Based Object Classification System for an Industrial Robotic Manipulator

Rasit Koker, Cemil Oz, Abdullah Ferikoglu

114

T2F

Threshold-Gates in Arithmetic Circuits

Christian Burwick, Marc Thomas, Karl Goser

116

M2A

The Real-Frequency Technique Applied to a Narrow Band MMIC Active Filter with Transmission Zero at Finite Frequencies

E. Kerherve, M. Hazouard, P. Jarry

117

T1P

Delay Estimation of SCL Gates With Output Buffer

Massimo Aliato, Gaetano Palumbo, Salvatore Pennisi

122

T1P

VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits

S. Perri, P. Corsonello, G. Cocorullo, G. Cappuccino, G. Staino

123

M3F

On the Design of Modulo 2n+-1 Adders

C. Efstathiou, H.T. Vergos, D. Nikolos

124

T1G

A New Class of Smith Predictors for Network Congestion Control

Peter Bauer, M. Sichitiu, R. Ernst, K. Premaratne

125

T1B

A Dynamic Thermal Management Circuit for System-on-Chip Designs

Herming Chiueh, J. Draper, J. Choma Jr.

126

W2B

An Improved Delay Compensation Technique for Digital Clock Recovery Loops

Fulvio Spagna

128

W1P

Electrocardiogram Characterization Using Wavelet Analysis

Karim Mokrani, A. Alliche

129

M1B

Efficient Sine Evaluation Architecture for Direct Digital Frequency Synthesis

L. Fanucci, R. Roncella, R. Saletti

130

M3D

Voice over IP over Satellite Links

Haitham Cruickshank, Antonio Sanchez, Zhili Sun

132

W1P

Bipartite Graph Labeling for the Subcircuit Recognition Problem

Nikolay Rubanov

133

T2F

An Area-Efficient Interpolation Filter Using Block Structure

Kyu Ha Lee, Dae Hee Youn, Chungyong Lee

134

W3B

An Improved Phase Clock Generator for Interleaved and Double-Sampled Circuits

Gabriele Manganaro

136

T1C

A method for Solving Stochastic Differential Equation with Random Coefficients

Takenobu Matsuura, Toshio Shinozaki

138

M1A

The Low Power Baseband Processing Parts of a Novel Dual Mode DECT/GSM Terminal

Christos Drosos, C. Dre, D. Metafas, D. Soudris, S. Blionas

139

M2P

About Linearization of Broadband Amplifier by Feedback (new opportunity of the well known method)

Yu. M. Bruck

140

M1A

An Optimally Self-Biased Threshold-Voltage Extractor

Siew Kuok Hoon, Ugur Cilingiroglu

141

T2D

A High Throughput 2-Dimensional DCT/IDCT Architecture for Real-Time Image and Video System

Jen-Shuin Chiang, Yi-Fang Chiu

142

W1P

Aperiodic Filter Analysis and Design by Symbolic Computation

A. Balestrino, G. Marani, L.Sani

143

T3E

Cascaded Feedforward Sigma-Delta Modulator for Wide Bandwidth Applications

Jen-Shiun Chiang, Pou-Chu Chou, Teng-Hung Chang

144

T1P

Training in the use of Java Smart Cards for Embedded Applications

L.T. Walczowski, F. Deravi

145

T1P

Distributed Simulation of VHDL Using Jini

J. Casal-Gimenez, L.T. Walczowski

146

M1D

Multi-Window Recursive Adaptive Neural Filters

Adrian Burian, Jukka Saarinen, Pauli Kuosmanen

148

M2F

Defect-Tolerance Design of the High-Speed RSA Encryption Processor with Built-in Table for Residue Calculation of Redundant Binary Numbers

Nobuhiro Tomabechi, Teruki Ito

149

W3D

Analysis of Microwave Frequency Dividers in Harmonic-Balance Simulators

A. Anakabe, J.M. Collantes, A. Suarez, J. Jugo, J. Portilla

151

W1E

SPU Based Microrobots: A New Approach to the Robotic World

Enric Montane, M. Puig-Vidal, J. Lopez-Sanchez, P. Miribel-Catala, S.A. Bota, J. Samitier

152

M2A

New High-Q Band-Pass Filter Configuration Using Current Controlled Current Conveyor Based All-Pass Filters

Ali Toker, Ece Olcay Gunes, Serdar Ozoguz

157

W1P

A Transform Domain Approach in Blocking Effect Detection

G.A. Triantafyllidis, D. Tzovaras, M.G. Strintzis

158

M2P

Design of Polysilicon TFT Operational Amplifier for Analog AMLCD Driver

C.L. Yiu, Philip K.T. Mok

159

T1P

Optimized Design of High Fan-in Multiplexers Using Switches With Driving Capability

Massimo Alioto, Gaetano Palumbo

161

M1F

Investigations of Online/Offline Test for Integrated Sensors in the Operating Phase

Michael Fischell, Andrew Weigl, Walter Anheier

162

M1B

A Difference Detector PFD for Low Jitter PLL

Kuo-Hsing Cheng, Tse-Hua Yau, Shu-Yu Jiang, Wei-Bin Yang

163

W1P

Bifurcation and Chaos in the Piecewise-Linear Forced Duffing-van der Pol Oscillator with a Diode

Naohiko Inaba, Kazutaka Tsukamoto

165

W1F

VLSI Implementation of CRC-32 for 10 Gigabit Ethernet

Tomas Henriksson, H. Eriksson, U. Nordqvist, P. Larsson-Edefors, D. Liu

166

T3E

Design and Implementation of an Audio Analog to Digital Converter Using Oversampling Techniques

S. Boujelben, Ch. Rebai, D. Dallet, Ph. Marchegay

170

W1P

Artificial Neural Network Applied to Electronic System Diagnostics

Jozef Drabarek, Robert Wirski

171

T3D

Delay-Sensitive Power Estimation at the Register-Transfer Level

Davide Bruni, G. Olivieri, L. Benini, A. Bogiolo

172

M2A

A Sampled-Analog Rank-Order Filter Architecture

Ugur Cilingiroglu, Luthuli Edem Dake

173

T3E

Clock Jitter Insensitive Continuous-Time Sigma-Delta Modulators

Maurits Ortmanns, Y. Manoli

174

M2P

Successful Design of Cascaded Continuous-Time Sigma-Delta Modulators

Maurits Ortmanns, Y. Manoli

175

M2B

New Design of Squarer Circuits using Booth Encoding and Folding Techniques

Davide de Caro, Antonio G.M, Strollo, Ettore Napoli

176

T1P

A Reconfigurable 2D Convolver for Real-Time SAR Imaging

Antonio G.M. Strollo, Ettore Napoli, Davide De Caro, Giacinto P. Saggese

177

T1P

Test Pattern Generator for Hybrid Testing of Combinational Circuits

Davide de Caro, Nicola Mazzocca, Ettore Napoli, Giacinto P. Saggese, Antonio G.M. Strollo

178

W2D

Maximum Power Supply Noise Estimation in Digital VLSI Circuits Using Multimodal Genetic Algorithms

G. Bai, S. Bobba, I.N. Hajj

179

T1C

Automated Flowgraph Analysis Using Matlab and Maple

T. Rahkonen, M. Neitola

182

M3G

High-Level Test Synthesis for Built-In Self-Testable Designs

Laurence Tianruo Yang, Jon Muzio

183

W1B

On the Feasibility of fT-Integration Employing Reverse-Active Vertical npns

Phanumas Khumsat, A. Worapishet, A.J. Payne

184

M1B

Phase Error Determination in GMSK Modulated Fractional-N PLL

Laurent Camino, Serge Ramet, Jean-Baptiste Begueret, Yann Deval, Pascal Fouillat

185

T3D

Analytical Current Model for Dual-Gate MOSFET

Koray Karahaliloglu, Gunhan Dundar

189

M2A

A Simple Design Technique for Multiple Resonance Networks

Antonio Carlos M. de Queiroz

191

M2P

A Two-Step Folder for a High-Speed CMOS Folding-and-Interpolating ADC

Sang Chan Han, Bumsoo Suh, Soo Won Kim

194

T1P

Deterministic Test Pattern Generation Unit Designs for Memory Built-In Self Test

A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, A. Arapoyanni

195

T3E

Design of a Wideband Transmit Delta-Sigma DAC

Marko Neitola, Arto Kivi, Timo Rahkonen

196

M2G

Unequal Processing Gain for JPEG2000 Image Transmission in a CDMA Environment

Marco Grangetto, Enrico Magli, Gabriella Olmo

197

W2C

On Area-Efficient Low Power Array Multipliers

Yingtao Jiang, Yuke Wang, Edwin Sha

198

M2P

A Novel BJT Output Stage for SAW Drivers

Kari Stadius, Petri Jarvio, Kari Halonen

199

W1P

A Wire Segment Reassignment Algorithm for Minimizing Crosstalk for Strait-Type River Routing

Jong-Sheng Cherng, Sao-Jie Chen

201

T3F

DSP Implementation of 3D Sound Localization Algorithm for Monaural Sound Source

N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa

202

T2F

A Novel Dynamically Programmable Arithmetic Array Using Code Division Multiple Access Bus

Boon-Keat Tan, Ryuji Yoshimura, Toshimasa Matsuoka, Kenji Taniguchi

203

W2F

FPGA Based On-line Complex Number Multiplier

Asun P. Pascual, Javier Valls, Trini Sansaloni

204

T2C

A Low Temperature Pipelined Analog-to-Digital Converter

Tuula K. Makiniemi, Paavo J. Kosonen

205

M1F

Stabilization of Power Consumption of the Heater of a Micromachined Silicon Gas Flow Sensor

A.A. Nassiopoulos, G. Kaltsas, A.G. Nassiopoulou

206

W3F

AUTODDM: AUTOmatic Characterization Tool for the Delay Degradation Model

J. Juan-Chico, M.J. Bellido, P. Ruiz-de-Clavijo, C. Baena, M. Valencia

207

M3C

Statistical Properties of Number Sequences Generated by 1D Chaotic Maps Considered as a Potential Source of Pseudorandom Number Sequences

Mieczyslaw Jessa, Marcin Walentynowicz

208

M2P

A New Architecture of CCK MODEM Based on Iterative Differential-Modulation and Phase-Detection

Tae-Ho Kim, Sang-Hun Yoon, Jong-Wha Chong

210

M3F

Distributed Arithmetic Radix-2 Butterflies for FPGA

Trini Sansaloni, A. Perez-Pascual, J. Valls

211

T1E

A Switching Current-Mode Power Stage Based on Sigma-Delta Modulation

Enrico Dallago, Marco Passoni, Gabriele Sassone, Giuseppe Venchi

213

M2P

A 1.5V 23MHz Low-Power FGMOS Filter

Esther O. Rodriguez-Villegas, Adoracion Rueda, Alberto Yufera

214

M2P

Dynamic Behavior of Dielectric Resonator Antennas

B.V. Lvov, V. Yu. Petrunkin

215

T1B

Novel Reconfigurable Two-MOSFET UV-programmable Floating-Gate Circuits for CARRY', NAND, NOR or INVERT functions

Snorre Aunet, Yngvar Berg, Oivind Naess, Trond Saether

216

W1P

Self-Adaptive Polling Protocols for Wireless LANs: A Learning-Automata-Based Approach

P. Nicopolitidis, G.I. Papadimitriou, A.S. Pomportsis

217

M3A

A CMOS Low Power Voltage Controlled Oscillator With Split-Path Controller

Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shuh-Shyuan Sheu

218

W2E

A 1.5V CMOS Square-Root Domain Filter

Antonio J. Lopez-Martin, Alfonso Carlosena

219

T1P

Unconditional Maximum Likelihood Approach for Near-Field Source Localization

Erdinc Cekli, Hakan A. Cirpan

221

W1P

Paradys: A Scalable Infrastructure for Parallel Circuit Simulation

Jean-Louis Lafitte, Y. Pizzuto

222

M1C

Decreasing the Minimal Sample Period for Recursive Filters Implemented Using Distributed Arithmetic

Oscar Gustafsson, Lars Wanhammer

223

M1C

Implementation of Bit-Parallel Lattice Wave Digital Filters With Increased Maximal Sample Rate

Henrik Ohlsson, Oscar Gustafsson, Hakan Johansson, Lars Wanhammer

224

W2B

Discrete-Time Randomized Sampling

Maya R. Said, Alan V. Oppenheim

226

W1P

A Control Strategy for Electromagnetic Near and Far Field Calculation

Jan Wilk, Horst Rohm

227

W3F

Application Boards Emulation Engine

Wadih Zaatar, George E. Nasr

228

M3A

A Current-Mode CMOS RMS-DC Converter for Very Low-Voltage Applications

Antonio J. Lopez-Martin, Alfonso Carlosena

229

W2C

Low-Power Logic Styles for Fulladder Circuits

J.M. Quintana, M.J. Avedillo, R. Jimenez, E. Rodriguez-Villegas

230

W3F

Verification of Combinational Circuits by Simulations, SAT, ATPG and BDDs

Katarzyna Radecka, Zeljko Zilic, Karim Khordoc

231

W1P

Self-synchronizing Watermark Detection for MPEG-4 Objects

Nikolaos V. Boulgouris, Filippos D. Koravos, M.G. Strintzis

232

T2C

MSB Steps Calibration Algorithm for a Pipelined ADC

Paavo J. Kosonen, Tero T. Suhonen

233

T3C

Non-Robust Delay Test Pattern Generation Based on Stuck-At TPG

Volker Meyer, Walter Anheier, Arne Sticht

235

W1P

Open Graphics Systems for 3D-Mapping Validation on Robotics

J.V. Catret, M. Mellado, D. Puig

236

W1P

An Iterative Method for Instantaneous Frequency Estimation

Aydin Akan, Mahmut Yalcin, Luis F. Chaparro

237

T1A

Accurate Current Mirror with High Output Impedance

Kuo-Hsing Cheng, Chi-Che Chen, Chun-Fu Chung

238

T1P

An Instrument with a DSP for Monitoring Human Biological Parameters

A. Buizza, G. Coldani, G. Danese, R. Gandolfi, P. Ghidetti, R. Lombardi

240

T3E

Differentially Randomized Quantization in Sigma-Delta Analog-to-Digital Converters

Holger Berndt, Hans-Joachim Jentschel

242

M1C

Estimation of Samples of the Derivative of a Signal Based on the Signal Difference Derivative

Ewa Hermanowicz

245

W3E

A 0.35um CMOS DCS Front-End with Fully Integrated VCO

Ellie Cijvat

246

W1F

How can Block Turbo Codes be Implemented?

Sylvie Kerouedan, Patrick Adde

247

M1F

The Design of CMOS Real-Time Motion-Direction Detection Chip with BJT-Based Silicon-Retina Sensors and Correlation-Based Motion Detection Algorithm

Chung-Yu Wu, Kuan-Hsun Huang

248

M1G

Control Strategy of a Solar Power Inverter (Analysis of a Seventh Order System)

K.H. Edelmoser, F.A. Himmelstoss

250

T2A

Electronically Tunable Current-Mode Second-Order Multifunctional Filter Using FTFNs and Dual-Output OTAs

Worapong Tangsrirat, S. Unhavanich, T. Dumawipata, W. Surakampontorn

251

M1F

CMOS Microsystem Front-End for MicroTesla Resolution Magnetic Field Measurement

Vincent Frick, Luc Hebrard, Philippe Poure, Francis Braun

252

W2F

Using a Hardware Coprocessor for Message Scheduling in Fieldbus-based Distributed Systems

Jose Fonseca, Paolo Neves, Ernesto Martins

256

M2G

Benchmark of Software Based MPEG-4 Video CODEC

Weiguo Zheng

257

T1P

Synchronization In DMT Based VDSL Modems

Abdelmonaem Lakhzouri, Markku Renfors

258

T3A

A Ready-to-Use Design Procedure for Operational Transconductance Amplifiers that Minimizes Power Consumption

A. Gerosa

259

M2P

A Ratio-Independent Algorithmic Pipeline Analog-to-Digital Converter

Shingo Hatanaka, Kenji Taniguchi

260

T2D

On the Digital Watermarking in JPEG 2000

M.A. Suhail, M.S. Obaidat

261

M1E

An Efficient and Precise Design Method to Optimize Device Areas in Mismatch and Flicker-Noise Sensitive Analog Circuits

Christian Paulus, Ralf Brederlow, Ulrich Kleine, and Roland Thewes

263

M3G

Object-Oriented High-Level Synthesis Based on SystemC

Eike Grimpe, Frank Oppenheimer

264

W2D

SPICE Model for the Single Electron Tunnel Junction

Rudie van de Haar, Roelof H. Klunder, Jaap Hoekstra

266

T1P

A 1.2V 500MHz 32-bit Carry-Lookahead Adder

Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang

267

T2E

On Placement and Routing of Wafer Scale Memory

Li-An Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu, Tai-Sheng Feng

269

W1D

A Selective Compression Algorithm for SAR Images Based on Irregular and Adaptive Sampling

Davide Avagnina, Fabio Dovis, Letizia Lo Presti, Paolo Mulassano

270

T2A

Synthesis of Companding Systems by Component to Component Substitution: an Alternative Method

Carlos A. De La Cruz Blas, Antonio J. Lopez Martin, Alfonso Carlosena

271

W1C

Generalized Symmetric Variables

Malgorzata Chrzanowska-Jeske

273

W1F

VLSI Implementation of Low Density Parity Check Decoder

W.L. Lee, Angus Wu, P. Li

275

T1P

Memory Efficient Pipelined Viterbi Decoder with Look-Ahead Trace Back

Jung-Gi Baek, Sang-Hun Yoon, Yong-Wha Chong

276

T3B

Parameter Identification of a DC Motor: An Experimental Approach

Samer S. Saab, Raed Abi Kaed-Bey

277

T1P

Analysis and Verification of Clock Distribution Network in the Presence of Switching Noise

M. Salim Maza, M. Linares Aranda

279

M2P

A Novel CMOS Charge Pump with Positive Feedback for PLL Applications

Esdras Juarez-Hernandez and Alejandro Diaz-Sanchez

281

T2C

A Successive Approximation A/D Converter with 16 bit 200 kS/s in 0.6 um CMOS using Selfcalibration and Low Power Techniques

Harald Neubauer, Thomas Desel, Hans Hauer

283

T1P

Designing Low-Power Energy Recovery Adders Based on Pass Transistor Logic

D. Soudris, V. Pavlidis, A. Thanailakis

284

M2P

An Optimised Design of an Improved Voltage Tripler

Ming Zhang, N. Llaser, F. Devos

287

M1B

A Hardware Efficient Direct Digital Frequency Synthesizer

Florean Curticapean, Jarkko Niittylahti

288

T2D

New Iterative Algorithms and Architectures of Modular Multiplication for Cryptography

O. Nibouche, A. Bouridane, N. Nibouche

289

T1A

Programmable Current Mode Circuits

Andrzej Mazurek, Krzysztof Wawryn

290

M2P

Implementation of current mode circuits for programmable neural network

Krzysztof Wawryn and Andrzej Mazurek

292

W2D

An Effective Procedure for Multi-tone Steady-State Analysis of Mixers

Robert Melville, Hans Georg Brachtendorf

294

W2D

A Practical Substrate Modeling Algorithm with Active Guardband Macromodel for Mixed-Signal Substrate Coupling Verification

Henry H.Y. Chan, Zeljko Zilic

295

T3D

An Accurate Poles-Zeros Analysis for Large-Scale Analog and Digital Circuits

Josef Dobes

296

W1P

Reducing Constructive Interference in ANC Systems by Selective Adaptation in the Frequency Domain

Longji Wang, Victor DeBrunner, Linda DeBrunner

300

W3E

A Direct-Conversion BiCMOS Mixer for GHz Application

Esa Tiiliharju, Kari Halonen

301

M3B

A Framework for A Wavelet-Based High Level Environment

Mokhtar Nibouche, A. Bouridane, O. Nibouche

302

W2B

Rapid Prototyping of Biorthogonal Discrete Wavelet Transforms On FPGAs

Mokhtar Nibouche, A. Bouridane, O. Nibouche

303

W3B

A CMOS Switched Capacitor Channel Select Filter For Direct Conversion UMTS Receiver

Bilal Manai, Patrick Loumeau

304

M1F

Fully Differential CMOS Programmable Analogue Sensor Interface Based on Fully Differential Multiple Differences Amplifiers

Antonio J. Gano, Nuno F.S. Especial

305

T3C

ESD Test Methods on Integrated Circuits: An Overview

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang

306

W3B

Design of a CMOS Fully Differential Switched-Opamp for SC Circuits at very Low Power Supply Voltages

J. Arias, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla

307

T1B

New Embedded Memory Architecture for Enhanced Yield, Performance and Power Consumption

Boris Polianskikh, Zeljko Zilic

311

T1F

A CMOS Piece-Wise Linear A/D Converter for Linearizing Sensor Characteristics

Antonio J. Lopez-Martin, Mikel Zuza, Alfonso Carlosena

313

W3C

A New Initialization Technique in Designing and Testing Phases of Clock-Free Circuits

Kaamran Raahemifar, Fei Yuan, Farahnaz A. Mahammadi

314

W2B

Fast 32-Bit Digital Multiplier

Kaamran Raahemifar, Majid Ahmadi

315

W1B

An Efficient 0-1 Linear Programming for Optimal PLA Folding

Kaamran Raahemifar, Majid Ahmadi

316

W2E

Antialiasing Filtering Influences on ADC Specifications for Radio Receivers

Elizabeth Colin, Patrick Loumeau, Lirida Naviner, Jean-Francois Naviner

318

T2E

A Study on the Relationship Between Initial Node-Edge Pairs Entropy and Mincut Circuit Partitioning

Kuo-Hsing Cheng, Shun-Wen Cheng

319

M2P

Layout Design on Multi-Finger MOSFET for On-Chip ESD Protection Circuits in a 0.18-um Salicided CMOS Process

Ming-Dou Ker, Che-Hao Chuang, Wen-Yu Lo, Yai-Line Dai, Ming-Huang Huang, Horng-Jyh Liu

320

M3B

Sampling Frequency Offset Estimation and Correction in OFDM Systems

Maja Sliskovic

321

T2A

Low-Sensitivity, Low-Power Fourth-Order Band-Pass Active-RC Allpole Filter Using Impedance Tapering

Drazen Jurisic, George S. Moschytz, Neven Mijat

324

W1D

A Transform Layered Signed Regressor Adaptive Filtering Algorithm

Dai I. Kim, Sung N. Choi, Sung H. Oh

325

M2C

Nonlinear Effects of RF Interference in MOS Operational Amplifiers

Franco Fiori, Paolo S. Crovetti

326

W3F

Design of Electric Filters in Maple and through WWW Interface

J. Bicak, J. Hospodka, J. Vrbata, P. Martinek

328

W3D

Dynamic Power of CMOS Gates Driving Lossy Transmission Lines

Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino

329

T3F

Power Reduction for Multimedia Applications Through Data-Reuse Memory Exploration

M. Kougia, A. Chatzigeorgiou, S. Nikolaidis

330

T1P

Power Exploration of Parallel Embedded Architectures Implementing Data-Reuse Transformations

N. Kavvadias, A. Zanikopoulos, Ch. Voliotidis, S. Kougia, A. Chatzigeorgiou, S. Nikolaidis

331

W1P

Windows in a Non-Autonomous Circuit with Symmetry

T. Miyoshi, M. Sekikawa, T. Sato, N. Inaba, Y. Nishio

332

W1D

Adaptive Filtering of Cyclostationary Interference From Speech

Olli Vuorinen, Tapio Seppanen, Jorma Lilleberg, Timo Kolehmainen, Juha Roning

333

W1F

Reconfigurable Coprocessor Based JPEG 2000 Implementation

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni

334

M2G

MPEG-4 Main Profile Decoder Partitioning with Respect to Bit Stream Processing

Kilian A. Jacob

338

T1E

Matched Filters for Identifying Failed Fuel Rods in Nuclear Reactors

J.M. Seixas, F.P. Freeland, W. Soares-Filho

339

M1D

Wavelet Transform as a Preprocessing Method for Neural Classification of Passive Sonar Signals

J.M. Seixas, D.O. Damazio, P.S.R. Diniz, W. Soares-Filho

340

T1P

Formal Verification of Digital Circuits by 3-Valued Simulation

Ayman M. Wahba and Einar J. Aas

341

T2B

Counting Up of Linear Lumped Parameter Systems and Their Unified Representation

Toshihiko Yamawaki

346

W1P

Fractal Image Coding Combined with Subband Decomposition

Katsutoshi Sawada, Shin-ya Nagai Eiji Nakamura

347

T2E

HDL Software Development and Hardware Prototyping of a System-on-Chip for an Active Filter Controller

Anna Labbe, Philippe Poure, Fabrice Aubepart, Francis Braun

348

W3D

A Moment Method Analysis of SAW Interaction in Periodic Metal-Semiconductor Structure

M.F. Elkordy, T.E. Taha, A. Gomaa

349

M2P

Current Conveyor Based Universal Biquad Filter

Maria Cristina Piccirilli

350

M3D

A Programmable Application-Specific VLSI Architecture for Speech Recognition

Jia-Ching Wang, Jhing-Fa Wang, An-Nan Suen, Yu-Sheng Weng

351

W1P

Chaotic and Hyperchaotic Synchronization of Two Nonautonomous and Nonlinear Electric Circuits

I.M. Kyprianidis and I.N. Stouboulos

352

T1A

Self-Calibrating Linear OTAs Exemplified in a Current Mode ADC

R. Wunderlich, R. Frieg, A. Dollberg, K. Schumacher

353

M2P

Fast CMOS Current Driver for IrDA - Applications

Hans W. Hauer

354

T2A

Dynamic Range Comparison of Voltage-Mode and Current-Mode State-Space Gm-C Biquad Filters

Slawomir Koziel, Stanislaw Szczepanski

355

W2F

Profit Evaluation System (PES) for Logic Cores at Early Design Stage

Shyue-Kung Lu, Tsung-Ying Lee

357

T1A

Lead Compensation to Improve the Stability of a Two Stage Rail-to-Rail CMOS Op Amp

Jean-Francois Delage, Mohamad Sawan

358

W1P

Text Analysis for the Slovenian Text-to-Speech System

Tomaz Sef

361

M1G

Sensorless Position Estimation Using Asymmetries in A.C. Machines

Cyril Spiteri Staines, Joseph Cilia

362

T1G

2.5-Gb/s 0.35-um CMOS ICs for Optic-Fiber Transceiver

Z.-G. Wang, X.-H. Chen, R. Tao, X.-M. Ke, J. Feng, T.-T. Xie, H.-T. Chen

363

T2E

Circuit Partitioning Techniques For Power Estimation Using The Full Set of Input Correlations

Ana T. Freitas, Arlindo L. Oliveira

364

M2C

A Topological Approach for Determining the Uniqueness of the DC Solution in MOS-Transistor Circuits

Arturo Sarmiento-Reyes, L. Hernandez-Martinez

365

W1P

Neural System For Military Target Detection

Adnan Khashman

368

T3B

Stability of Discrete Time-Variant Linear Delay Systems and Applications to Network Control

Mihail L. Sichitiu, Peter Bauer

369

T1D

Unifying Metric Approach to Classification for Three Classes

Tony Y. T. Chan

370

M2P

High Frequency Threshold Improvement of Electro-static Micro-relays

G.I. Efremov and N. I. Mukhurov

371

W2A

Chip Design of a Bandpass Sigma-Delta Modulator

Sau-Mou Wu, Rou-Yi Liu, Wei Wu

372

W1E

A Resonant Transmission Energy transformer to a Non-Invasive Rechargeable Battery for Artificial Organs

Toshi Hiro Nishimura, Tetsuji Eguchi, Akira Kubota, Kazuhiko Hamamoto

373

M1G

Minimum Settling Time Voltage Regulation of Single-Phase PFC Converters

Predrag Ninkovic, Zarko Janda

374

M1C

A Regularized Digital Filtering Technique for the Simultaneous Reconstruction of a Function and its Derivatives

Marcelino Lazaro, Ignacio Santamaria, Carlos Pantaleon

375

M2E

I/O Buffer Placement Methodology for ASICs

Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm

376

W3E

Design and Implementation of Decimation Filter Cascade for Radio Communications

Khaled Grati, Adel Ghazel, Lirida Naviner, Faker Moatamri

378

T1B

Two-Dimensional Array Layout for NMOS 4-Phase Dynamic Logic

Makoto Furuie, Takao Onoye, Shuji Tsukiyama, Isao Shirakawa

379

W2B

DSP and ASIC Implementation of Pulse Shape Filter for 3G Wireless TDD Systems

R. Veljanovski, J. Singh, M. Faulkner

380

T1F

A Scintillator-coated Phototransistor Pixel Sensor with Dark Current Cancellation

Munir A. Abdalla, Ervin Dubaric, C. Frojdh, C.S. Petersson

381

M2D

A Serial-Parallel Architecture for Wavelet Image Compression

A. Masoudnia, H. Sarbazi-Azad, S. Boussakta

382

W3D

A New Mobility Model for Pocket Implanted Quarter Micron n-MOSFET's and Below

Peter Klein

383

W2A

Novel Noise Shaping of Cascaded Sigma-Delta Modulator for Wide Bandwidth Applications

Jen-Shiun Chiang, Teng-Hung Chang, Pou-Chu Chou

385

W1E

A New Approach for Mobile Manipulator Motion Control

Foudil Abdessemed, Eric Monacelli, Khier Benmahammed

386

T3A

A Comparative Study of Low-Voltage Performance of Standard Cell Flip-Flops

Xue Shang, Bengt Oelmann

389

M3C

Theoretical Connection Between PN-Sequences and Chaos Makes Simple FPGA Pseudo-Chaos Sources Possible

Andras Mozsary, Leonardo Azzinari, Karol Krol, Veikko Porra

390

M2P

Associated Resistive and Discrete Circuits in the Qualitative Analysis of Networks of Distributed and Lumped Circuits

Antonio Maffucci and Giovanni Miano

392

T1F

Adaptive Interference Reduction in Nerve Cuff Electrode Recordings

Iasonas Triantis, Robert Reiger, John Taylor, Nick Donaldson

393

M2B

A Single Latch, High Speed Double-Edge Triggered Flip-Flop (DETFF)

Troy A. Johnson, Ivan Kourtev

395

T1P

Fault-Tolerance-Based Computation of Global Functions in Asynchronous Distributed Systems

Hossam M.A. Fahmy and Abubakr A. El-Hefnawy

397

M2P

A Mixed-Mode Perception Cell for VLSI Neural Networks

Fausto Camboni and Maurizio Valle

398

M2P

A Smart "Single Line" Pixel Sensor for Industrial Vision

Eric Senn, D. Emzivat, E. Martin

399

M1E

Automatic Methodology for Placing the Guard Rings into Chip Layout to Prevent Latchup in CMOS IC's

Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh

400

M3G

Architectural Synthesis of Digital Signal Processing Applications Dedicated to Submicron Technologies

Christophe Jego, Emmanuel Casseau, Eric Martin

401

W1P

Improvements to SPIHT for Lossy Image Coding

Jian Zhu and Stuart Lawson

403

M1B

Fully Integrated CMOS Phase Locked Loop with 30MHz to 2GHz Locking Range and +/-35ps Jitter

Chao Xu, Winslow Sargeant, Kenneth Laker, Jan Van der Spiegel

404

M2E

Distributed Evolutionary Design of Constant-Coefficient Multipliers

D. Chen, T. Aoki, N. Homma, T. Higuchi

408

M3A

Delay/Slope Budgeting for Clock Buffer Cell Design

Qing K. Zhu

409

M1A

A Novel Wide-Band CMOS Current Amplifying Cell and Its Application in Power Supply Current Monitoring

Srdjan Dragic, Martin Margala, Igor M. Filanocsky

410

M3B

Design of M-Band Optimal Orthonormal Wavelet of Compact Support for Signal De-Noising by Using the Principle of Complexity Regularization

A. Das, U.B. Desai, P.P. Vaidya

411

W2A

A Comparative Study of Digital Sigma-Delta Modulator for Fractional-N Synthesizer

Keliu Shu, Udaykiran Eduri, Edgar Sanchez-Sinencio, Franco Maloberti

413

M3G

Data-Driven Process Decomposition for the Synthesis of Asynchronous Circuits

Catherine G. Wong, Alain J. Martin

414

M2P

The Influence of Model Parameters on Accurate IMD Simulations in HBTs

Phillip Wong and Branimir Pejcinovic

416

W2F

A 250-MHz, 32-Bit Quantum MOS Correlator Prototype

Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. Gonzalez, Pinaki Mazumder

417

T1E

Design of an Electric Vehicle for the Maltese Islands

Cyril Spiteri Staines, Joseph Cilia, Victor Buttigieg

418

W2A

On the Stability of High Order Sigma-Delta Modulators

Valeri Mladenov, Hans Hegt, Arthur van Roermund

420

M3D

Phoneme Classification in Hardware Implemented Neural Networks

Edward Gatt, Joseph Micallef, Paul Micallef, Edward Chilton

422

W3D

Fast Characterization of RTL Power Macromodels

M. Anton, I. Colonescu, E. Macii, M. Poncino

424

M2C

Feedback-Amplifiers: A Simplified Analysis of Harmonic Distortion in the Frequency Domain

Gaetano Palumbo, Salvatore Pennisi

425

T3F

Fast Algebraic Convolution for Prime Power Lengths

Reiner Creutzburg, Torsten Minkwitz

427

W3E

A 0.35 SiGe BiCMOS Front End for GSM Low IF Cellular Receiver Applications

L. Dermentzoglou, G. Kamoulakos, A. Arapoyanni

428

W2C

Comparison of Static Logic Styles for Low-Voltage Digital Design

Mika Kontiala, Mika Kuulusa, Jari Nurmi

429

M2P

Influence of Local Matching Effects on the Accuracy of a Sequential A/D Converter

Alexander Dollberg, J. Oehm, R. Wunderlich, K. Schumacher

430

T3A

Current-Controlled Policies for Battery-Driven Dynamic Power Management

Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino

431

M2F

Bit-Level Architectures for Montgomery's Multiplication

O. Nibouche, A. Bouridane, M. Nibouche

435

M3C

Experiments on Chaotic Circuits and Crypted Data Transmission

Giovanna Lombardo, Giuseppe Lullo, Rosalia Zangara

436

T3D

A Method for Simulation of Floating-Gate UV-Programmable Circuits With Application to Three New 2-MOSFET Digital Circuits

Snorre Aunet, Yngvar Berg, Trond Ytterdal, Oivind Naess, Trond Saether

437

W3B

Switch Sizing for Very Low-Voltage Switched-Capacitor Circuits

Mohamed Dessouky, M. -M. Lauerat, A. Kaiser

438

W1C

Signal Identification by Nonlinear Optimization

Pavel Popela, Jaroslav Sklenar

439

M1E

IC Design Automation from Circuit Level Optimization to Retargetable Layout

Xu Jingnan, J. Serras, M. Oliveira, R. Belo, M. Bugalho, J. Vital, N. Horta

441

T2C

D/A Conversion: Amplitude and Time Error Mapping Optimization

Konstantinos Doris, Chieh Lin, Arthur van Roermund, Domine Leenaerts

443

W3C

Concurrent BIST Cost Estimation During Data Path Allocation

Haidar M. Harmanani

444

T3A

Design Optimization of Low-Voltage Current-Mode Integrators for Low-Power Continuous-Time Sigma-Delta Modulators

Hassan Aboushady, Marie-Minerve Louerat

446

T2F

A Code Transformation-Based Methodology for Improving I-Cache Performance

N. Liveris, N.D. Zervas, C.E. Goutis

448

W3E

Noise Contribution in a Fully Integrated 1-V, 2.5-GHz LNA in CMOS-SOI Technology

Carlo Tinella, J.M. Fournier, J. Haidar

449

T2D

JPEG 2000: Finite Precision Representation and Hardware Implications

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni

450

W1F

Effects of Analogue ACS Implementation Errors on the Modified Feedback Decoding Algorithm

Andreas Demosthenous, John Taylor

451

M3G

A Divider-Multiplier High Level Synthesis Library Element for DSP Applications

V. Rodellar, M.A. Sacristan, A. Diaz, V. Peinado, P. Gomez

453

W2A

Analysis of Bandpass Sigma-Delta Converters in OFDM Systems

Antonio Moschitta, Dario Petri

454

M2P

A True Logarithmic Analog-to-Digital Pipeline Converter with 1.5 bit/stage and Digital Correction

Jorge Guilherme, Joao Vital, Jose Epifanio de Franca

455

M2P

A Distributed Transducer System for Functional Electrical Stimulation

Gunnar Gudnason, Jannik H. Nielsen, Erik Bruun

456

T1D

Associative Amplitude Modulation with Built-In Noise Immunity

Ron Spencer, Huseyin Dinc, Taner Sumesaglam

457

W3C

An Efficient Test Vector Compression Technique Based on Geometric Shapes

Salif al Zahir, Aiman El-Maleh, Esam Khan

458

T3F

On the Numerical Accuracy of CORDIC-based Frequency Offset Compensation in Burst Oriented OFDM Systems

L.D. Kabulepa, T. Kella, T. Pionteck, R. Ludewig, J. Becker, J. Plechinger, M. Glesner

459

W1A

Integrated Front-End Preamplifier Dedicated to Ultrasonic Receivers

R. Chebli, A. Kassem, M. Sawan

460

T2A

High Frequency CMOS Gm-C Bandpass Filter with Automatic On-Chip Tuning

H. Elhallabi, Y. Fouzar, M. Sawan

461

T2B

On-line Digital Correction of the Harmonic Distortion in Analog-to-Digital Converter

U. Eduri, F. Maloberti

462

W1F

A Fast CRC Implementation on FPGA Using a Pipelined Architecture for the Polynomial Division

Fabrice Monteiro, Abbas Dandache, Amine M'Sir, Bernard Lepley

463

W1E

An Implantable CMOS Amplifier for Nerve Signals

Jannik Hammel Nielsen, Torsten Lehmann

464

W2F

Design Verification of an 18 Million-Transistor Digital Television and Media Processor Chip

Santana Dutta

465

T1G

An Adaptive Call Admission Control Algorithm in Integrated Services Networks

Lu Guoying, Li Zemi

466

M3C

Control of Chaotic Behavior by Parameter Commutation Methodology

A.I. Mahla, L. Torres

469

T2B

Fuzzy Rank Ordering for Robust Multiuser Detection in Non-Gaussian Channels

Joan Bas, Ana Perez-Neira

471

T3B

A Reconfigurable Linear Feedback Shift Register (LFSR) for the Bluetooth System

Paris Kitsos, N. Sklavos, N. Zervas, O. Koufopavlou

472

W3C

Design of On-line Reconfigurable Datapaths Using Self-Checking Circuits

A.P. Kakarountas, V. Kokkinos, C.E. Goutis

473

M2B

Programmable Logic Using a SET Electron Box

Roelof H. Klunder, Jaap Hoekstra

474

W2C

A Novel Low Power Multiplexer-Based Full Adder Cell

Bassem Alhalabi, Adbulkarim Al-Sheraidah, Hung Tien Bui

475

T1P

Five New High-Performance Multiplexer-Based 1-Bit Full Adder Cells

Bassem Alhalabi, Adbulkarim Al-Sheraidah, Hung Tien Bui

476

T1P

Conditional Techniques for Small Power Consumption Flip-Flops

Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija

479

W2C

Asynchronous Low Power Implementation of the International Data Encryption Algorithm

Nikos Sklavos, Odysseas Koufopavlou

481

T1D

A New Light-Activated CMOS Retinal-Pulse Generation Circuit Without External Power Supply for Artificial Retinal Prostheses

Chung-Yu Wu, Li-Ju Lin, Kuan-Hsun Huang

482

T1E

Multipulse High Power Factor Rectifier Applying a Novel Current Injection Network

Zarko Janda, Predrag Pejovic

484

W2B

On Signal Resconstruction from Fourier Magnitude

Gil Michael, Mosche Porat

485

T2D

Two-Dimensional Joint Process Adaptive Filter via the Sparse Support Region for Image Restoration

Dai I. Kim, P. De. Wilde

486

T1D

Autoassociative Memory Using Refractory Period of Neurons and Its On-line Learning

Mikio Oda, Hiromi Miyajima

487

T1P

A Gate-Level Timing Model for SOI Circuits

Mehrdad Shahriari and Farid N. Najm

488

T3A

Class AB Output Stages for Low Voltage CMOS Op Aamps with Accurate Quiescent Current Control by Means of Dynamic Biasing

A. Torralba, R.G. Carvajal, J. Ramirez-Angulo, J. Tombs, J.A. Galan

489

M1G

Performance of Power Converters at Cryogenic Temperatures

Malik E. Elbuluk, Ahmad Hammoud, Scatt Gerber, Richard L. Patterson

490

T1F

Electrical Characterization and Modeling of Thin-Film Humidity Sensors

A. Bonavita, A. Caddemi, N. Donato, P. Accordino, S. Galvagno, G. Neri

491

M2D

A Parallel 3D DCT Architecture for the Compression of Integral 3D Images

Amar Aggoun, I. Jollah

492

M3B

ECG Compression Algorithm Based on Coding and Energy Compaction of the Structure Of The Wavelet Coefficients

Mohammed Abo-Zahhad, Bashar Rajoub

493

M2D

A Low Power SIMD Architecture for Affine-Based Texture Mapping

Wael Badawy

495

W1A

Maximizing Bandwidth in CCII for Wireless Optical Applications

Luis Nero Alves, Rui L. Aguiar

496

T1P

VLSI Architectures for Blind Equalization Based on Fractional-Order Statistics

V. Paliouras, J. Dagres, P. Tsakalides, Thanos Stouraitas

497

W3C

A Test Bed for Wireless Optical LANs

Rui L. Aguiar, Antonio Tavares, Luis N. Alves, Rui Valadas, Denis M. Santos

498

W1E

Design of a Portable Microprocessor-Based Stimulator for the Recreation of Impaired Gastrointestinal Motility

Y. Lin, L.E. Turner, M.P. Mintchev

499

T2E

A General Class of Passive Macromodels for High-Speed Distributed Interconnects

Anestis Dounavis, Ram Achar, Michel Nakhla

500

W1A

A Feedforward Compensation Scheme for High Gain, Wideband Amplifiers

Bharath Kumar Thandri S., Jose-Silva Martinez, Franco Maloberti

501

M3D

Transcoding Techniques for Translating GSM to G.729 Speech Coding Standards

Shu-Min Tsai, Jar-Ferr Yang

502

W2E

Signal Detection and Processing of Seismic Electromagnetic Radiation in ELF Band

503

M2G

Memory Hierarchy Layer Assignment for Data Re-Use Exploitation in Multimedia Algorithms Realized on Predefined Processor Architectures

K. Masselos, F. Catthoor, C.E. Goutis, H. De Man

504

W1A

A 1.8 GHz CMOS Low-Noise Amplifier

Carl James Debono, Franco Maloberti, Joseph Micallef

506

W1E

Mechanical and Control System Design of a Dexterous Robotic Gripper

Claire Seguna, Michael Saliba

507

T1D

Hardware Radial Basis Functions Neural Networks for Phoneme Recognition

Edward Gatt, Joseph Micallef, Edward Chilton

511

T2G

Stand-By Low-Power Architecture in a 3V-Only 2-Bit/Cell 64-Mbit Flash Memory

Rino Micheloni, Ilaria Motta, Osama Khouri and  GuidoTorelli

512

T2G

TDNVRAMTM: Methodology and Architecture of a Non-Volatile-Memory Technology Development Testchip

D. Montanari, D. DeShazo and G. Yeric

513

T2G

Modular architecture for a Family of Multilevel 256/192/128/64 Mbit 2Bit/Cell 3V-Only NOR Flash Memory Devices

Andrea Silvagni, Stefano Zanardi, Alessandro Manstretta, Marco Scotti, Luca Crippa, Giancarlo Ragone, Giuseppe Fusillo, Giovanni Campardo, Osama Khouri and Marcello Stefanelli

514

T2G

A New Flash Memory Sense amplifier in 0.18 um CMOS Technology

A. Chrisantopoulos, Y. Moisiadis, A. Varagis, Y. Tsiatouhas and A. Arapoyanni

515

T2G

Optimized Programming of Multilevel Flash EEPROMs

Roberto Versari, David Esseni, Gianluca Falavigna, Massimo Lanzoni and  Bruno Riccò

516

W3A

Advances in Low-Voltage Low-Power Analog IC Design

W. Serdijn, L.C.C. Marques, J. Mulder

517

W3A

Low-Power Low-Voltage Library Cells and Memories

C. Piguet, J.M. Masgonty, S. Cserveny, C. Arm

518

W3A

1-V CMOS Class AB Current Mirror

S. Pennisi

519

W3A

Low-Voltage Low-Power Adaptive Biased High-Efficiency Integrated Amplifiers

G. Ferri

520

W2G

A New Way of Information Extraction from QMB Sensors in Air and in Liquid

D. Vitaglione, C. Di Natale, C. Falconi, D. D'Amico, G. Ferri, A. D'Amico

521

W1G

A Comparison between Feature Extraction Methods of Electronic Nose Responses

C. Distante, P. Siciliano

522

W2G

A Wind Sensor with an Integrated Low-Offset Instrumentation Amplifier

K.A.A. Makinwa, J.H. Huijsing

523

W1G

Leakage Localization with a Mobile Robot Carrying Chemical Sensor

M. Wandel, U. Weimar, A. Lilienthal, A. Zell

524

W1G

High-Density Microelectrode Arrays for Electrophysiological Activity Imaging of Neuronal Networks

L. Berdondini, T. Overstolz, N.F. de Rooij, M. Koudelka-Hep, M. Aany, P. Seitz

525

W1G

E-Beam Patterned Nanoelectrodes for Electrochemical Applications

O.T. Guenat, L. Berdondini, S. Gautsch, M. Gullo, U. Staufer, N.F. de Rooij, M. Koudelka-Hep

526

W2G

A CMOS ASIC for Differential Read-Out of ISFET Sensors

L. Ravezzi, D. Stoppa, M. Corra, G. Soncini, G.F. Dalla Betta, L. Lorenzelli

527

W2G

ANGELO Evaluation: Application of a Multisensor System for Psycho-Physiological Stress Detection in Working Environments

F. Davide, M. Russo, M. Gutknecht, S. Ganci, A. Avamini, M. Holmberg, M. Andersson, M. Nardi. A. Pede, A. Colosimo, A. D'Amico, C. Di Natale, V. Spicacci

528

T3G

Modeling of Fractional-N Division Frequency Synthesizers with SIMULINK and MATLAB

S. Brigati, F. Francesconi, M. Poletti, A. Malvasi

529

T3G

Saturation Recovery Technique for High-Order Bandpass Switched-Capacitor Sigma-Delta Modulators

P. Casinato, F. Pasolini, F. Stefani, A. Baschirotto

530

T3G

A Novel Architecture to Reduce Complexity in HD Read Channels Based on Fractionally Spaced Equalization

Andrea Gerosa, Andrea Neviani, Andrea Xotta, Gain Antonio Mian

531

T3G

Analog CMOS Implementation of Feature Detection Operators for Automatic Real-Time Optical Character Recognition Systems

D.D. Caviglia, M. Tosato, M. Mazzucco, G.M. Bo, M. Valle

532

T3G

Low-Voltage Low-Power Novel CCII Topologies and Applications

G. Ferri, N. Guerrini

533

M3E

Requirements for Embedded Data Converters in an ADSL Communication System

H. Casier

534

M3E

Design of High-Speed Analog to Digital Interface in Digital CMOS Technology

K. Uyttenhove, M. Steyaert

535

M3E

Design Considerations for High-Resolution Pipeline ADCs in Digital CMOS Technology

J. Guilherme, P. Figueiredo, P. Azevedo, G. Minderico, A. Leal, J. Vital, J. Franca

536

M3E

A High-Performance Sigma-Delta ADC for ADSL Applications in 0.35 um CMOS Digital Technology

R. del Rio, J.M. de la Rosa, F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez

537

M3E

Design Solutions for Low-Power Digital Filters

R. Rossi, G. Torelli, V. Liberali

540

T1G

Self-Routing Crossbar Switch with internal Contention Resolution

Christoph Heer, Andreas Kirstaedter, Christian Sauer

541

W1A

Low Voltage Programmable Current Mode Circuit for Onset Detection in a Sound Signal

Ivan Grech, Joseph Micallef, Tanya Vladimirova

542

W2E

Low Voltage Log Domain Front End for the Extraction of 2-D Sound Localization Cues

Ivan Grech, Joseph Micallef, Tanya Vladimirova

543

M1A

Second Order Mash Delta-Sigma FDM-Solution with Adaptive Improvements

Monica Finsrud, Mats Hovin, Tor Sverre Lande