ELE 3103 - Hardware Description Languages (HDL)

Credits:   2 
Lectures/Tut.:   8 hrs 
Labs:   6 hrs 
Prerequisite:   none 
Leads to:   ELE 3102, CCE 3202

Objectives
The module introduces hardware description languages (mainly VHDL) as a tool for describing and synthesizing logic circuits in the process of digital design automation. During the lab sessions, the students will familiarise themselves with the process of digital integrated circuit synthesis, together with place and route, starting from HDL code to silicon level. 

Syllabus

• Introduction to the design methodology using hardware description languages.
• Structural, concurrent and sequential VHDL descriptions, subprograms, VHDL operators, signals and variables, variable types,  WAIT statements and sensitivity lists.
• Simulation of VHDL models, test benches, debugging - outputting to the console.
• Design organisiation and parameterisation: subprograms, packages, default, fixed and generic parameters, design configuration, general purpose test benches.
• Delay modeling and timing issues.
• Dataflow description in VHDL: multiplexers, Moore and Mealy FSMs, open collector gates.
• Brief introduction to Verilog HDL, comparison with VHDL. 

Laboratory Work      
Design of a digital circuit starting from a HDL description using Xilinx XC4000X FPGA chips. Also familiarisation with Cadence simulation, synthesis and place and route tools for digital chip design.

Assessment
Coursework - 25% 
Exam - 75%

Textbook

• Zainalabedin Navabi, VHDL, Analysis and Modeling of Digital Systems, McGraw-Hill, ISBN 0-07-112732-1.

Reading List

• Lewin Douglas & Protheroe David, Design of Logic Systems, Chapman & Hall, ISBN 0-412-42890-3.